Many types of integrated circuits (ICs) contain programmable elements. Programmable logic devices (PLDs) are an example of ICs that contain programmable elements. PLDs are digital, user-configurable integrated circuits. PLDs include an array of logic elements and programmable interconnect circuitry. The logic elements can be programmed to implement logic functions. Logic functions are created by selectively coupling the logic elements of the PLD. The ability to program the logic elements and the interconnect circuitry provides the user with a high degree of flexibility to implement a multitude of custom logic functions of varying complexity.
Programming software is typically used in cooperation with PLDs to perform design entry, design compilation, and verification. The programming software is also used to program the PLD once the design has been compiled and verified. For more information on PLDs and programming software, see the 1996 Data Book from Altera Corporation, San Jose, Calif., which is incorporated by reference herein.
One advantage of using PLDs is the ability to perform in-system programming (ISP). ISP allows users to program and re-program PLDs that have been incorporated into digital systems, such as a PLD soldered onto a printed circuit board. PLDs are commonly implemented in embedded systems. An embedded system is a computer or microprocessor system which is not a general purpose computer workstation, but a system dedicated to a particular function within some larger electronic system. Embedded systems often do not have the peripheral devices and I/O devices that are common on general purpose desktop computers, like keyboards, video displays, and disk drives.
There are two common applications for in-system device programming in an embedded system. One is to program new devices in a new system during the manufacturing process. The other is to re-program devices with an updated version of a pattern, possibly long after the system was manufactured and sold to the end customer. This is known as an "in-field upgrade". In both cases, the programmable device and the computer or microprocessor performing the programming operation (the "host") typically reside together in the same electronic system.
A number of methods to perform ISP are known. Most of these ISP methods rely on a modified version of the IEEE Standard 1149.1--JTAG Boundary Scan Test Procedure (hereafter referred to as JTAG-BST) to perform the ISP. The JTAG-BST standard is described in "IEEE Std. 1149.1-1990, IEEE Standard Test Action Port and Boundary Scan Architecture", published by the Institute of Electrical and Electronics Engineers, which is incorporated by reference herein.
The JTAG-BST is used to insure that the integrated circuits on a printed circuit board are properly mounted and interconnected. To perform a JTAG-BST, the printed circuit board manufacturer generates a serial vector format (SVF) file for the board under test. The SVF file is created from a group of standard instructions defined by the SVF format. An automatic test equipment (ATE) system which interfaces with the integrated circuits on the board, then provides the vectors of the SVF file to the integrated circuits on the board. The vectors pass through boundary scan registers on the integrated circuits, causing certain signals to be generated at the input and output pins of the integrated circuits under test. The ATE system then compares the actual signals generated at the input and output pins with the expected signals to determine if a mounting and/or interconnect problem exists on the board. For more information on JTAG-BST and SVF files, see "Boundary Scan Testing" by Harry Blecker, Kluwer Academic Publishers, 1993 and the Serial Vector Format Specification developed by Texas Instruments, September 1994, both of which are incorporated by reference herein.
As indicated above, programming software can be used to perform ISP. With this method, a programming object file (POF) is loaded onto the computer running the programming software. The POF is a file that contains all the address locations and the programming information needed to configure the PLD to assume the logic function defined by the user. The programming software then takes the data in the POF and generates vectors including instructions and control information which cause the PLD to sequence through its programming modes. To initiate programming, the vectors are down-loaded from the computer to the board containing the PLD via a serial cable that is compliant with the JTAG-BST interface, causing the PLD to be programmed. Although this ISP method is simple, it is relatively slow and therefore is typically used only for design and prototyping, not for large scale production.
ISP is also performed using ATE systems which are normally used to perform JTAG-BST, such as the IC test equipment from Teradyne. The ATE is provided with an SVF file that has been modified to include: (1) address information identifying selected elements in the PLD to be programmed; (2) data to indicate how to program the selected elements; and (3) control information to cause the PLD to sequence through its programming modes so that the selected elements are programmed in accordance with the data. The ATE then down-loads the vectors of the modified SVF file to the PLD for programming. Since the modified SVF file is in the same format as the SVF file used for JTAG-BST, the programming is "transparent" to the ATE. Note that with certain ATE's, such as the HP3070 from Hewlett-Packard, a translated SVF file is provided to the ATE.
Yet another method of ISP involves the use of an embedded processor on the board containing the PLD to be programmed. A modified SVF file, containing the same address, data, and control information as described above, is provided to the embedded processor. The embedded processor then downloads the vectors in the modified SVF file to program the PLD. Since the processor is embedded in the system, this type of ISP can be readily performed in the field by a customer or end user.
There are a number of problems related to using modified SVF files for programming PLDs. SVF files modified for programming PLDs tend to be extremely large because each instruction in the file must include the address to be programmed and the programming data in order to be compliant with the SVF specification. Modified SVF files also tend to be very large because they often contain duplicate copies of the same address and programming data. For example, if the modified SVF file contains information to program a PLD and information to perform two verification tests to confirm the programming of the PLD, then the SVF file essentially contains three copies of the address and programming data. Lastly, since the SVF format was developed for JTAG-BST, the vectors of the file can only be serially executed. Adaptive programming, such as the use of conditional branches, are not permitted under the SVF specification. As a consequence, modified SVF files tend to be cumbersome and inflexible, which makes them less than ideal for ISP. Other problems with SVF include the fact that SVF cannot represent a time delay in real time, only in terms of a number of clock cycles, SVF does not guarantee a particular "path" through the JTAG state machine when making a transition from one state to another, and SVF does not allow some particular state transitions which might be needed for device programming.
In view of the foregoing, it would be highly desirable to provide an improved technique for in-system programming of integrated circuits containing programmable elements.